Method of manufacturing an alignment mark

ABSTRACT

A silicon-on-insulator (SOI) substrate having a grid-line region and a circuit region, and including a silicon substrate having an upper surface, a first insulating layer having an upper surface and a silicon layer, and which has a grid-line region zoning a circuit region. An element isolation region is formed in the silicon layer of the circuit region of the SOI substrate, and an insulating region is formed in the silicon layer of the grid-line region of the SOI substrate. The insulating region and a portion of the first insulating layer located under the insulating region are removed to define a recess in the grid-line region.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of manufacturing analignment mark of a semiconductor device, and more particularly, to amethod of manufacturing an alignment mark which is used in an alignmentbetween plural layer patterns when a multitiered structure semiconductordevice is formed.

[0003] The present application claims priority under 35 U.S.C. §119 toJapanese Patent Application No. 2001-159214, filed May 28, 2001, whichis herein incorporated by reference in its entirely for all purposes.

[0004] 2. Description of the Related Art

[0005] A conventional method of manufacturing an alignment mark isdisclosed in, for example, Japanese Laid-Open Patent Publication-:HEI06-021406, published on Jan. 28, 1994.

[0006]FIG. 7 is a flow chart showing a conventional process formanufacturing an alignment mark, in the case of a silicon-on-insulator(SOI) semiconductor structure.

[0007] First, as shown in a step 701, an SOI substrate is formed. Therepresentative methods of manufacturing the SOI substrate are bondingtechnology methods and oxide ion implantation methods. In bondingtechnology, a silicon wafer having an oxide layer is bounded to anothersilicon wafer which does not have an oxide film. On the other hand, inoxide ion implantation, an oxide ion is implanted into a silicon wafer,and then a high-temperature thermal treatment is performed.

[0008] Next, as shown in step 702, a photolithography using an alignmentfor an element isolation pattern is performed, and a resist patternhaving openings is generated. The openings of the resist pattern arelocated at alignment mark regions and vernier regions. Next, as shown ina step 703, a silicon etching is performed to remove the SOI layer (thesilicon layer) of the SOI wafer at locations of the alignment markregions and the vernier regions, using a second resist pattern as amask. Next, as shown in a step 704, a resist peeling is performed toremove the second resist.

[0009] Then, a positioning is performed using the alignment mark formedas above, and the positioning is confirmed using the vernier.

[0010] More specifically, the following process steps are usually usedfor an SOI structure wafer (an SOI wafer) having the element isolationpattern.

[0011] (1) A forming step of the element isolation pattern. (Isolationregions are formed.)

[0012] (2) A forming step of the bond SOI wafer. (Bonding and polishingare performed.)

[0013] (3) A forming step of the semiconductor device.

[0014] An input into the step (3) after a termination of the step (2) isreferred to a line re-input. The SOI layer located at the alignmentregions and the vernier regions of the SOI wafer having the elementisolation pattern are etched during the line re-input. As a result,sufficient level differences of these regions are ensured. The SOI layerat other regions (e.g. an element formation region) is masked by theresist pattern, and are not etched. Therefore, a photolithography stepof aligning the lower element isolation pattern is required. At thistime, it is possible to sufficiently detect a signal waveform indicativeof the alignment mark for following reasons:

[0015] (1) A top layer of the alignment mark and vernier regions isdifferent from that of the element isolation region. The top layer ofthe alignment mark and vernier regions is consisted of a silicon oxide(SiO₂), on the other hand, the top layer of the element isolation regionis a silicon (Si).

[0016] (2) A range of tolerance with respect to deviation in thealignment is large. At this time, a fine alignment of 0.15 μm is notrequired, and about 2.0 μm is sufficient.

[0017] As a result, a clear signal waveform indicative of the alignmentmark is obtained. Specifically, since a sufficient level difference ofthe alignment mark region can be secured, a signal waveform having asufficient S/N ratio can be obtained.

[0018] The alignment mark which is used to the manufacturing process ofthe semiconductor device having such an SOI structure, is formed byremoving the SOI layer of the alignment mark region by etching. However,a thickness of the SOI layer is gradually being reduced to achievecertain technical device advantages (e.g. high integration, highfunctionality, low power supply voltage, etc.). Therefore, differencesin the alignment mark region decrease more and more. As a result, asignal waveform having a sufficient S/N ratio can not be obtained, andit becomes difficult to accurately detect such an alignment mark.

SUMMARY OF THE INVENTION

[0019] According to one aspect of the present invention, in a method ofmanufacturing an alignment mark, a silicon-on-insulator (SOI) substrateis provided having a grid-line region and a circuit region, andincluding a silicon substrate having an upper surface, a firstinsulating layer having an upper surface and a silicon layer, an elementisolation region is formed in the silicon layer of the circuit region ofthe SOI substrate, an insulating region is formed in the silicon layerof the grid-line region of the SOI substrate, the insulating region anda portion of the first insulating layer located under the insulatingregion are removed to define a recess in the grid-line region.

[0020] According to the present invention, since the alignment markconstructed with a deep concave portion, the alignment mark can bedetected with a high degree of accuracy in various alignment steps.

[0021] The above and further objects and novel features of the inventionwill more fully appear from the following detailed description, appendedclaims and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] While the specification concludes with claims particularlypointing out and distinctly claiming the subject matter which isregarded as the invention, it is believed that the invention, theobjects and features of the invention and further objects, features andadvantages thereof will be better understood from the followingdescription taken in connection with the accompanying drawings in which:

[0023]FIG. 1 is a plan view showing a semiconductor wafer which isobtained by a method of manufacturing an alignment mark according to afirst preferred embodiment of the present invention;

[0024]FIG. 2 is a cross-sectional view along the line 2-2′ in FIG. 1 ofan alignment mark region (a grid-line) between circuit regions;

[0025] FIGS. 3(a) through 3(e) are cross-sectional views showing amethod of manufacturing an alignment mark according to the firstpreferred embodiment of the present invention;

[0026] FIGS. 4(a) through 4(d) are cross-sectional views showing amethod of manufacturing an alignment mark according to the firstpreferred embodiment of the present invention;

[0027] FIGS. 5(a) through 5(e) are cross-sectional views showing amethod of manufacturing an alignment mark according to a secondpreferred embodiment of the present invention;

[0028] FIGS. 6(a) through 6(d) are cross-sectional views showing amethod of manufacturing an alignment mark according to a third preferredembodiment of the present invention; and

[0029]FIG. 7 is a flow chart showing a process sequence according to aconventional method of manufacturing an alignment mark.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Preferred embodiments of the present invention will hereinafterbe described in detail with reference to the accompanying drawings. Thedrawings used for this description typically illustrate majorcharacteristic parts in order that the present invention will be easilyunderstood.

[0031]FIG. 1 is a plan view showing a semiconductor wafer 10 which isobtained by a method of manufacturing an alignment mark 1 according to afirst preferred embodiment of the present invention. As shown FIG. 1,the semiconductor wafer 10 having an SOI structure includes theplurality of circuit regions 2, an alignment mark region 3 (thegrid-line 3) and the alignment mark 1. The grid-line 3 is locatedbetween the plurality of circuit regions 2. The alignment mark M isformed on the grid-line 3. In a semiconductor manufacturing process, thegrid-line 3 divide the semiconductor wafer 10 is divided into aplurality of semiconductor chip regions.

[0032]FIG. 2 is a cross-sectional view along the line 2-2′ in FIG. 1 ofan alignment mark region 3 (a grid-line 3) between circuit regions 2. Asshown in FIG. 2, the semiconductor wafer 10 is constructed with asilicon substrate 11, a silicon oxide layer 12 and a silicon layer 13(an SOI layer 13). A thickness of the silicon oxide layer 12 is about120 nm. The SOI layer 13 includes a plurality of element isolationregions 14, and a thickness of the SOI layer 13 and the elementisolation regions 14 is about 40 nm. The alignment mark 1 is located atthe grid-line 3, and is formed as a concave portion in which the siliconoxide layer 12 and the element isolation layers 14 are removed. At thistime, a depth of the alignment mark 1 is about 160 nm, which is equal tothe combined thickness of the removed layer 12 and region 14.

[0033] A semiconductor device is formed in the circuit region 2 byperforming sequentially, for example, a film-forming process, aphotolithography process which transcribes and forms a resist patternindicating a circuit pattern, and an etching process using the resistpattern as a mask.

[0034] In the photolithography process, at first, a resist materialconsisting of a photosensitive polymeric material is coated on thesemiconductor wafer. Then, the circuit pattern is exposed by irradiatingan ultraviolet rays to the resist material, using a glass mask which hasa light blocking pattern consisting of, for example, chromium. In suchan exposure process, it is absolutely necessary to align and expose thewafer with a high degree of accuracy. Then, the resist pattern havingthe circuit pattern is formed by developing the exposed resist material.

[0035] Next, the method of manufacturing of the alignment mark accordingto the first preferred embodiment of the present invention will bedescribed below.

[0036] FIGS. 3(a) through 3(e) and FIGS. 4(a) through 4(d) arecross-sectional views showing a method of manufacturing an alignmentmark 1 according to the first preferred embodiment of the presentinvention. As shown in FIG. 3(a), the silicon oxide layer is formed inthe silicon substrate 11 of the semiconductor wafer 10. At this time, athickness of the silicon oxide layer 12 is, for example, 120 nm, and athickness of the silicon layer 13 (the SOI layer 13) which is located onthe silicon oxide layer 12 is, for example, 40 nm. Then, the elementisolation regions 14 of silicon oxide are formed in the silicon layer 13by a local oxidation of silicon (LOCOS) process. Specifically, anelement isolation regions 14 d are formed within the circuit region 2,and an element isolation region 14 m is formed within the grid-line 3.

[0037] As shown in FIG. 3(b), a resist layer 15 is formed on the SOIlayer 13 having the element isolation regions 14. Such a resist layer 15is obtained by exposing a resist material which is coated on the SOIlayer 13 and the element isolation layer 14. The resist layer 15 isformed over the circuit region 2 with an opening over the grid-line 3.

[0038] As shown in FIG. 3(c), the element isolation region 14 m of thegrid-line 3 and the silicon oxide layer located under the elementisolation region 14 m, are removed by an alternative etching using theresist layer 15 and the SOI layer 13 of the grid-line 3 as a mask. Thealternative etching is preformed using a mixed gas including 30 sccmCHF₃, 150 sccm Ar and 2 sccm O₂, at normal temperatures and under 4 Papressure. The term sccm denotes a gas mass flow (cm³/m) per a minute ata normal condition. As a result, the alignment mark 1 is constructedhaving a concave portion formed in the grid-line 3.

[0039] As shown in FIG. 3(d), the resist layer 15 is removed. At thistime, a depth of the alignment mark 1 (the concave portion) is about 160nm.

[0040] As shown in FIG. 3(e), a poly-silicon layer 17, a tungstensilicide layer 18 and a nitride layer 19 are formed sequentially, afteran oxide layer 16 is formed on the SOI layer 13 and the siliconsubstrate 11 of the grid-line 3. The poly-silicon layer 17 and thetungsten silicide layer 18 are used to form a gate electrode. Then, aresist layer 20 is formed on the nitride layer 19 by coating of a resistmaterial. The resist layer 20 is used in a subsequent photolithographyprocess.

[0041] Thereafter, the semiconductor wafer 10 is transported into anexposure apparatus, and then, for example, a halogen light or a laserlight is exposed onto a device surface of the semiconductor wafer 10. Inthe device surface, the above mentioned various layers have been formedat previous process steps. Such an exposed light is reflected anddiffracted at boundaries between the various layers, and at a differenceof the alignment mark 1. The exposure apparatus detects strength of therefracted light and the diffracted light and outputs an output signalindicating the strength of the light. At this time, the exposureapparatus detects a position of the alignment mark 1 and aligns thesemiconductor wafer 10.

[0042] Since the alignment mark 1 is constructed with a deep concaveportion, a diffused reflection of the alignment mark 1 is larger thanthat of other regions. Therefore, the alignment mark 1 can be detectedwith a high degree of accuracy. More further, since the position of thesemiconductor wafer 10 is adjusted on the basis of the alignment mark 1,the semiconductor wafer 10 can be correctly aligned.

[0043] Next, another example of the first preferred embodiment of thepresent invention will be described below. FIGS. 4(a) through 4(d) showthe another example of the first preferred embodiment of the presentinvention.

[0044] As shown in FIG. 4(a), a resist pattern 20 g which is used toform the gate electrode, is formed at the circuit region 2.Specifically, the resist pattern 20 g is formed by subjecting the resistlayer 20 to the photolithography process (the exposure and developmentprocess).

[0045] As shown in FIG. 4(b), the nitride layer 19, the tungstensilicide layer 18, the poly-silicon layer 17 and the oxide layer 16 areremoved sequentially by an etching process using the resist pattern 20 gas a mask. The etching of the nitride layer 19 is performed using amixed gas including 20 sccm C₄F₈, 10 sccm O₂ and 400 sccm Ar, at normaltemperatures and under 5.3 Pa pressure. The etching of the tungstensilicide layer 18 is performed using a mixed gas 20 sccm Cl₂ and 2 sccmO₂, at 60° C. temperature and 0.7 Pa pressure. The etching of thepoly-silicon layer 17 is performed by using a mixed gas 20 sccm Cl₂ and7 sccm O₂, at 60° C. temperature and 0.7 Pa pressure. As a result, theoxide layer 16 g, the poly-silicon layer 17 g, the tungsten silicidelayer 18 g and the nitride layer 19 g remain under the resist pattern 20g, in the circuit region 2.

[0046] On the other hand, in the grid-line 3, since the alignment mark 1is constructed with a deep concave portion, a side wall 23 including theoxide layer 16, the poly-silicon layer 17, the tungsten silicide layer18 and the nitride layer 19 is formed on a side surface of the alignmentmark 1. As a result, an alignment mark 100 is constructed with a deepconcave portion and complex concave and convex portions at a peripheryof the deep concave portion. A configuration of the complex concave andconvex portions is variable in accordance with a thickness of the abovementioned layers 17, 18 and 19, and the etching conditions.

[0047] As shown in FIG. 4(c), the gate electrode including the oxidelayer 16 g, the poly-silicon layer 17 g, the tungsten silicide layer 18g and the nitride layer 19 g is exposed upon removing the resist pattern20 g.

[0048] As shown in FIG. 4(d), an interlayer isolating layer 21 is formedon the semiconductor wafer 10. Then, a resist layer 22 is formed on theinterlayer isolating layer 21 by coating of a resist material. Theresist layer 22 is used in a subsequent photolithography process.

[0049] Thereafter, the semiconductor wafer 10 is transported into anexposure apparatus, and then, for example, a halogen light or a laserlight is exposed to a device surface of the semiconductor wafer 10. Inthe device surface, the above mentioned various layers have been formedat previous process steps. Such an exposed light is reflected anddiffracted at boundaries between the various layers, and at a differenceof the alignment mark 100. The exposure apparatus detects strength ofthe refracted light and the diffracted light and outputs an outputsignal indicating the strength of the light. At this time, the exposureapparatus detects a position of the alignment mark 1 and aligns thesemiconductor wafer 10.

[0050] Since the alignment mark 100 is constructed with a deep concaveportion, a diffused reflection of the alignment mark 100 is larger thanthat of another regions. Therefore, the alignment mark 100 can bedetected with a high degree of accuracy. More further, since theposition of the semiconductor wafer 10 is adjusted on the basis of thealignment mark 100, the semiconductor wafer 10 can be correctly aligned.

[0051] According to the first preferred embodiment of the presentinvention, since the oxide layer 12 and the element isolating layer 14which are formed on the silicon substrate 11 are removed by theselective etching, the alignment mark 1 constructed with a deep concaveportion can be obtained. Therefore, the alignment mark 1 can be detectedwith a high degree of accuracy. More further, since the alignment mark100 can maintain the deep concave portion when the gate electrode isformed, the alignment mark 100 can be detected with a high degree ofaccuracy in subsequent alignment steps.

[0052] FIGS. 5(a) through 5(e) are cross-sectional views showing amethod of manufacturing an alignment mark according to a secondpreferred embodiment of the present invention. The second preferredembodiment includes the same process steps as shown in FIGS. 3(a)through 3(e) of the first preferred embodiment. A process step as shownin FIG. 5(a) is performed after a process step as shown in FIG. 3(e).

[0053] As shown in FIG. 5(a), a resist pattern 30 covering over thecircuit region 2 is formed.

[0054] As shown in FIG. 5(b), the nitride layer 19 located at thegrid-line 3 is removed by an etching process using the resist pattern 30as a mask. Therefore, the tungsten silicide layer 18 located at thegrid-line 3 is exposed. Then, the resist pattern 30 is removed.

[0055] As shown in FIG. 5(c), the resist pattern 20 g which is used toform the gate electrode, is formed in the circuit region 2.

[0056] Next, the nitride layer 19, the tungsten silicide layer 18, thepoly-silicon layer 17 and the oxide layer 16 are removed sequentially byan etching process using the resist pattern 20 g as a mask. On the otherhand, in the grid-line 3, since the alignment mark 1 is constructed witha deep concave portion, a side wall 24 including the poly-silicon layer17 and the tungsten silicide layer 18 is formed on a side surface of thealignment mark 1. Then, the resist pattern 20 g is removed. As a result,as shown in FIG. 5(d), the gate electrode is obtained including the gateelectrode including the oxide layer 16 g, the poly-silicon layer 17 g,the tungsten silicide layer 18 g and the nitride layer 19 g, and analignment mark 200 is constructed with a deep concave portion, areobtained. Since the side wall 24 does not include the nitride layer 19,a bottom surface of the alignment mark 200 is larger than that of thealignment mark 100 of the first preferred embodiment, and also theconcavity of the alignment mark 200 has a greater volume (and is moreeasily detected) than that of the alignment mark 100.

[0057] As shown in FIG. 5(e), the interlayer isolating layer 21 isformed on the semiconductor wafer 10. Then, the resist layer 22 isformed on the interlayer isolating layer 21 by coating ofa resistmaterial. The resist layer 22 is used in a subsequent photolithographyprocess.

[0058] Thereafter, the semiconductor wafer 10 is transported into anexposure apparatus, and then, for example, a halogen light or a laserlight is exposed to a device surface of the semiconductor wafer 10. Inthe device surface, the above mentioned various layers have been formedat previous process steps. Such an exposed light is reflected anddiffracted at boundaries between the various layers, and at a differenceof the alignment mark 200. The exposure apparatus detects a strength ofthe refracted light and the diffracted light and outputs an outputsignal indicating the strength of the light. At this time, the exposureapparatus detects a position of the alignment mark 200 and aligns thesemiconductor wafer 10.

[0059] Since the alignment mark 200 is constructed with a deep concaveportion, a diffused reflection of the alignment mark 200 is larger thanthat of other regions. Therefore, the alignment mark 200 can be detectedwith a high degree of accuracy. More further, since the position of thesemiconductor wafer 10 is adjusted on the basis of the alignment mark200, the semiconductor wafer 10 can be correctly aligned.

[0060] According to the second preferred embodiment of the presentinvention, since the nitride layer 19 in the grid-line 3 is removed bythe etching process before the gate electrode is formed, the side wall24 does not include the nitride layer 19. As a result, since a bottomsurface of the alignment mark 200 is larger than that of the alignmentmark 100 of the first preferred embodiment, and also the concavity ofthe alignment mark 200 is has a greater volume (and is more easilydetected) than that of the alignment mark 100. Therefore, the alignmentmark 200 can be detected with a high degree of accuracy in subsequentalignment steps.

[0061] FIGS. 6(a) through 6(d) are cross-sectional views showing amethod of manufacturing an alignment mark according to a third preferredembodiment of the present invention. The third preferred embodimentincludes the same process steps as shown in FIGS. 3(a) through 3(e) ofthe first preferred embodiment. A process step as shown in FIG. 6(a) isperformed after the process step as shown in FIG. 3(e).

[0062] As shown in FIG. 6(a), the resist pattern 20 g is formed in thecircuit region 2, and a resist pattern 20 m is formed in the grid-line2.

[0063] As shown in FIG. 6(b), the nitride layer 19, the tungsten suicidelayer 18, the poly-silicon layer 17 and the oxide layer 16 are removedsequentially by an etching process using the resist patterns 20 g and 20m as a mask. As a result, the oxide layer 16 g, the poly-silicon layer17 g, the tungsten silicide layer 18 g and the nitride layer 19 g remainunder the resist patterns 20 g and 20 m.

[0064] As shown in FIG. 6(c), the resist patterns 20 g and 20 m areremoved. As a result, the gate electrode including the oxide layer 16 g,the poly-silicon layer 17 g, the tungsten silicide layer 18 g and thenitride layer 19 g is formed in the circuit region 2. Also, an alignmentmark 300 constructed with a deep concave portion which is filled with ofthe stacked oxide, poly-silicon, tungsten silicide and nitride layers16, 17, 18 and 19, is formed in the grid-line 3.

[0065] As shown in FIG. 6(d), the interlayer isolating layer 21 isformed on the semiconductor wafer 10. Then, the resist layer 22 isformed flatly on the interlayer isolating layer 21 by coating of aresist material. The resist layer 22 is used in a subsequentphotolithography process.

[0066] Thereafter, the semiconductor wafer 10 is transported into anexposure apparatus, and then, for example, a halogen light or a laserlight is exposed to a device surface of the semiconductor wafer 10. Inthe device surface, the above mentioned various layers have been formedat previous process steps. Such an exposed light is reflected anddiffracted at boundaries between the various layers, and at a differenceof the alignment mark 300. The exposure apparatus detects a strength ofthe refracted light and the diffracted light and outputs an outputsignal indicating the strength of the light. At this time, the exposureapparatus detects a position of the alignment mark 300 and aligns thesemiconductor wafer 10.

[0067] Since the alignment mark 300 is constructed with a deep concaveportion, a diffused reflection of the alignment mark 300 is larger thanthat of another regions. Therefore, the alignment mark 300 can bedetected with a high degree of accuracy. More further, since theposition of the semiconductor wafer 10 is adjusted on the basis of thealignment mark 300, the semiconductor wafer 10 can be correctly aligned.

[0068] According to the third preferred embodiment of the presentinvention, since the oxide, poly-silicon, tungsten silicide and nitridelayers 16, 17, 18 and 19 remain in the grid-line 3 when the gateelectrode is formed, the alignment mark 300 constructed with the deepconcave portion can be obtained. Therefore, the alignment mark 300 canbe detected with a high degree of accuracy in subsequent alignmentsteps.

[0069] While the present invention presents an example in which thealignment mark is a rectangle as shown in FIG. 1, the invention is notlimited to this example and the form of the alignment mark isselectable.

[0070] Further, while the present invention presents an example in whichthe alignment mark constructed with the concave portion (the negativetype) is used, the present invention is not limited to this example andan alignment mark constructed a convex portion (a positive type) may beused.

[0071] The present invention has been described with reference toillustrative embodiments, however, this invention must not be consideredto be confined only to the embodiments illustrated. Variousmodifications and changes of these illustrative embodiments and theother embodiments of the present invention will become apparent to thoseskilled in the art with reference to the description of the presentinvention. It is therefore contemplated that the appended claims willcover any such modifications or embodiments as fall within the truescope of the invention.

What is claimed is:
 1. A method of manufacturing an alignment mark,comprising: providing a silicon-on-insulator (SOI) substrate having agrid-line region and a circuit region, and including a silicon substratehaving an upper surface, a first insulating layer having an uppersurface which is formed on the upper surface of the silicon substrate,and a silicon layer which is formed on the upper surface of the firstinsulating layer; forming an element isolation region in the siliconlayer of the circuit region of the SOI substrate; forming an insulatingregion in the silicon layer of the grid-line region of the SOIsubstrate; and removing the insulating region and a portion of the firstinsulating layer located under the insulating region to define a recessin the grid-line region.
 2. The method according to claim 1, wherein therecess exposes the upper surface of the silicon substrate.
 3. The methodaccording to claim 1, wherein the element isolation region and theinsulating region are formed in a same oxidation process.
 4. The methodaccording to claim 1, wherein the insulating region and the portion ofthe first insulating layer are removed by etching using the siliconlayer as a mask.
 5. The method according to claim 1, further comprises:forming a second insulating layer over an upper surface of the siliconlayer and within the recess; forming a conductive layer over the secondinsulating layer; forming a third insulating layer over the conductivelayer; forming a first resist pattern over the third insulating layer;and removing portions of the second and third insulating layers and theconductive layer, by an etching process using the resist pattern as amask.
 6. The method according to claim 1, further comprises: forming asecond insulating layer over an upper surface of the silicon layer andwithin the recess; forming a conductive layer over the second insulatinglayer; forming a third insulating layer over the conductive layer;forming a first resist pattern over the third insulating layer coveringover the circuit region; removing a portion of the third insulatinglayer located at the grid-line region by an etching process using thefirst resist pattern as a mask; exposing a remaining portion of thethird insulating layer at the circuit region by removing the firstresist pattern; forming a second resist pattern over the exposed thirdinsulating layer located at the circuit region; and removing the secondand third insulating layers and the conductive layer, by an etchingprocess using the second resist pattern as a mask.
 7. The methodaccording to claim 1, further comprises: forming a second insulatinglayer over an upper surface of the silicon layer and within the recess;forming a conductive layer over the second insulating layer; forming athird insulating layer over the conductive layer; forming a first resistpattern over the third insulating layer, the first resist patterndefining circuit patterns in the circuit region and covering thegrid-line region; and removing portions of the second and thirdinsulating layers and the conductive layer, by an etching process usingthe first resist pattern as a mask.
 8. A method of manufacturing analignment mark, comprising: providing a silicon-on-insulator (SOI)substrate having a grid-line and a circuit region, and including asilicon substrate having an upper surface, a first oxide layer having anupper surface which is formed over the upper surface of the siliconsubstrate, and a silicon layer which is formed over the upper surface ofthe first oxide layer; forming an element isolation region in thesilicon layer of the circuit region of the SOI substrate; forming anoxide region in the silicon layer of the grid-line region of the SOIsubstrate; removing the oxide region and a portion of the first oxidelayer located under the oxide region to define a recess in the grid-lineregion.
 9. The method according to claim 8, wherein the recess exposesthe upper surface of the silicon substrate.
 10. The method according toclaim 8, wherein the element isolation region and the oxide region areformed in a same oxidation process.
 11. The method according to claim 8,wherein the oxide region and the portion of the first oxide layer areremoved by etching using the silicon layer as a mask.
 12. The methodaccording to claim 8, further comprises: forming a first insulatinglayer over an upper surface of the silicon layer and within the recess;forming a conductive layer over the first insulating layer; forming asecond insulating layer over the conductive layer; forming a firstresist pattern over the second insulating layer; and removing portionsof the first and second insulating layers and the conductive layer, byan etching process using the resist pattern as a mask.
 13. The methodaccording to claim 8, further comprises: forming a first insulatinglayer over an upper surface of the silicon layer and within the recess;forming a conductive layer over the first insulating layer; forming asecond insulating layer over the conductive layer; forming a firstresist pattern over the second insulating layer covering over thecircuit region; removing a portion of the second insulating layerlocated at the grid-line region by an etching process using the firstresist pattern as a mask; exposing a remaining portion of the secondinsulating layer at the circuit region by removing the first resistpattern; forming a second resist pattern over the exposed secondinsulating layer located at the circuit region; and removing the firstand second insulating layers and the conductive layer, by an etchingprocess using the second resist pattern as a mask.
 14. The methodaccording to claim 8, further comprises: forming a first insulatinglayer over an upper surface of the silicon layer and within the recess;forming a conductive layer over the first insulating layer; forming asecond insulating layer over the conductive layer; forming a firstresist pattern over the second insulating layer, the first resistpattern defining circuit patterns in the circuit region and covering thegrid-line region; and removing portions of the first and secondinsulating layers and the conductive layer, by an etching process usingthe first resist pattern as a mask.